On Wafer Reliability Test Bench for PHEMT and HBT Technologies

Fast reliability testing is a key point for IlI-V technologies. This is particularly true when modifications have to be implemented on the production line. Such modifications can be soned in four categories: raw material, new equipment, prncess slep and design rule modifications. Endurance tests have to be performed to ensure that through the modified steps the reliability of the technology has not been changed. High Temperature Operating Life-tests (HTOL) is h e common way of assessing the reliability of active devices like field-effect transistors, diodes or varactors. For Ill-V devices, these tests are usually done on packaged chips. The devices are completely processed including the full front-end and a complete backend process with wafer thinning, viahole etching, dicing and packaging. Knowing that in a standard process-flow the active devices are generally processed before the passive elements (inductor, resistor, capacitor) and before the backside, the time delay between the active devices' process completion and the reliability testingcould take weeks. A quicker reliability feedback can be obtained by testing the devices directly on wafer after the front-side completion. In the frame of this "time-to-answer" redoction, we have developed a Wafer Level Reliability (WLR) test system that is able to handle all the UMS technologies: MESFET, lownoise PHEMT, Power PHEMT and HRT. This system can stress devices at different temperatures (Tcase=25"C up to Tcase=200"C) for different bias points and perform Ule intermediate measurements without removing the wafer from the system. This allows a fast assessment of the electrical parameters' drifts and therefore a quick evaluation of the modification on reliability.